وریلاگ

//-----------------------------------------------------------------------------
//
// Title : a
// Design : ahad
// Author : Gerdoo.net
// Company : Gerdoo
//
//-----------------------------------------------------------------------------
//
// File : a.v
// Generated : Sat Dec 17 10:08:05 2016
// From : interface description file
// By : Itf2Vhdl ver. 1.22
//
//-----------------------------------------------------------------------------
//
// Description :
//
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps

//{{ Section below this comment is automatically maintained
// and may be overwritten
//{module {a}}
module div_b_3 (clk,reset,out);
//}} End of automatically maintained section
parameter s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100, s5=3'b101;
input clk,reset;
wire clk,reset;
output out;
reg out;
reg[2:0] state,nstate=3'b000;
always @(state,clk,reset)
case(state)
s0:
begin
assign out=1'b1;
nstate=s1;
end
s1:
begin
assign out=1'b1;
nstate=s2;
end
s2:
begin
assign out=1'b1;
nstate=s3;
end
s3:
begin
assign out=1'b0;
nstate=s4;
end

s4:
begin
assign out=1'b0;
nstate=s5;
end

s5:
begin
assign out=1'b0;
nstate=s0;
end
default
begin
assign out=1'b0;
nstate=s5;
end
endcase
always @(clk)
state=nstate;

// -- Enter your statements here -- //

endmodule
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