module pilot(hw,cty,x,clk,reset);
output reg[1:0]hw,cty;
input x;
input clk;
input reset;
reg [2:0]state,next_state;
parameter red=2'd0,yellow=2'd1,green=2'd2;
parameter s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100, s5=3'b101;
parameter y2r=2'b11,r2g=2'b10;
always @(state,x,reset)
if(reset==1'b1)
next_state=s0;
else
case(state)
s0: next_state=x?s1:s0;
s1: begin
repeat(y2r)
@(posedge clk);
next_state=s2;
end
s2: begin
repeat(r2g)
@(posedge clk);
next_state=s3;
end
s3:next_state=x?s3:s4;
s4:begin
repeat(y2r)
@(posedge clk);
next_state=s5;
end
s5:begin
repeat(r2g)
@(posedge clk);
next_state=s0;
end
default:next_state=s0;
endcase
always @(state)
case(state)
s0:{hw,cty}={green,red};
s1:{hw,cty}={yellow,red};
s2,s5:{hw,cty}={red,red};
s3:{hw,cty}={red,green};
s4:{hw,cty}={red,yellow};
default:{hw,cty}={green,red};
endcase
always @(posedge clk)
state=next_state;
endmodule
module test1;
wire[1:0]hw1,cty1;
reg x1;
reg clk,reset;
pilot sc(hw1,cty1,x1,clk,reset);
initial
$monitor($time,"main_signal=%b,hw=%b,cty=%b",hw1,c ty1,x1);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
reset=1'b1;
repeat(5)@(negedge clk);
reset=1'b0;
end
initial
begin
x1=1'b0;
#200 x1=1'b0;
#100 x1=1'b1;
#200 x1=1'b0;
#100 x1=1'b1;
#200 x1=1'b0;
#100 x1=1'b1;
#100 $stop;
end
endmodule
