کد تقسیم فرکانس

module divf(out1,clk,reset);
input reset,clk;
output reg out1;
parameter s0=4'b0000,s1=4'b0001,s2=4'b0010,s3=4'b0011,
s4=4'b0100,s5=4'b0101,s6=4'b0110,s7=4'b0111,s8=4'b 1000,
s9=4'b1001;
reg [3:0]state,n_state;
always @(state,reset)
if(reset==1'b1)
{n_state,out1}={s0,1'b0};
else
case(state)
s0: {n_state,out1}={s1,1'b0};
s1: {n_state,out1}={s2,1'b0};
s2: {n_state,out1}={s3,1'b1};
s3: {n_state,out1}={s4,1'b1};
s4: {n_state,out1}={s5,1'b1};
s5: {n_state,out1}={s6,1'b1};
s6: {n_state,out1}={s7,1'b1};
s7: {n_state,out1}={s8,1'b1};
s8: {n_state,out1}={s9,1'b1};
s9: {n_state,out1}={s0,1'b1};
default:{n_state,out1}={s0,1'b0};
endcase

always @(clk)
state=n_state;


endmodule